fix pc for 2 byte instructions
This commit is contained in:
327
riscv64.cc
327
riscv64.cc
@@ -55,19 +55,33 @@ enum Op {
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BLT,
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BLTU,
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BNE,
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C_ADD,
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C_ADDI,
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C_ADDIW,
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C_ADDI16SP,
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C_ADDI4SPN,
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C_BEQZ,
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C_BNEZ,
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C_EBREAK,
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C_FLDSP,
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C_JALR,
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C_LD,
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C_LDSP,
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C_LI,
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C_LUI,
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C_LW,
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C_MV,
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C_SD,
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C_SDSP,
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C_SLLI,
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C_SW,
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DIV,
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DIVU,
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DIVUW,
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DIVW,
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ECALL,
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FENCE,
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FENCE_TSO,
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JAL,
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JALR,
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LB,
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@@ -75,6 +89,7 @@ enum Op {
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LD,
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LH,
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LHU,
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LR_D,
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LUI,
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LW,
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LWU,
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@@ -84,11 +99,13 @@ enum Op {
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MULW,
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OR,
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ORI,
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PAUSE,
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REM,
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REMU,
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REMUW,
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REMW,
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SB,
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SC_D,
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SD,
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SH,
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SLL,
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@@ -116,6 +133,8 @@ enum Op {
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struct Ins {
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Op op;
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u8 length;
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u8 rd;
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u8 rs1;
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union {
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@@ -131,49 +150,117 @@ struct Section {
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u64 entrypoint;
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};
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enum class Format { NONE, R, I, I_LOAD, I_SHIFT, S, B, U, J, CI, CSS, CR };
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enum class Format {
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NONE,
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R,
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I,
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I_LOAD,
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I_SHIFT,
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S,
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B,
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U,
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J,
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CI,
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CSS,
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CR,
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CL,
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R_ATOMIC,
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R_ATOMIC_LR
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};
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struct OpDef {
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const char *mnemonic;
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Format format;
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};
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static constexpr std::array<OpDef, 71> OP_TABLE = {{
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{"???", Format::NONE}, {"add", Format::R},
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{"addi", Format::I}, {"addiw", Format::I},
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{"addw", Format::R}, {"and", Format::R},
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{"andi", Format::I}, {"auipc", Format::U},
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{"beq", Format::B}, {"bge", Format::B},
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{"bgeu", Format::B}, {"blt", Format::B},
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{"bltu", Format::B}, {"bne", Format::B},
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{"c.addi", Format::CI}, {"c.addi16sp", Format::CI},
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{"c.addi4spn", Format::CI}, {"c.li", Format::CI},
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{"c.lui", Format::CI}, {"c.mv", Format::CR},
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{"c.sdsp", Format::CSS}, {"c.slli", Format::CI},
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{"div", Format::R}, {"divu", Format::R},
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{"divuw", Format::R}, {"divw", Format::R},
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{"ecall", Format::NONE}, {"jal", Format::J},
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{"jalr", Format::I}, {"lb", Format::I_LOAD},
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{"lbu", Format::I_LOAD}, {"ld", Format::I_LOAD},
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{"lh", Format::I_LOAD}, {"lhu", Format::I_LOAD},
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{"lui", Format::U}, {"lw", Format::I_LOAD},
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{"lwu", Format::I_LOAD}, {"mul", Format::R},
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{"mulh", Format::R}, {"mulhu", Format::R},
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{"mulw", Format::R}, {"or", Format::R},
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{"ori", Format::I}, {"rem", Format::R},
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{"remu", Format::R}, {"remuw", Format::R},
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{"remw", Format::R}, {"sb", Format::S},
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{"sd", Format::S}, {"sh", Format::S},
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{"sll", Format::R}, {"slli", Format::I_SHIFT},
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{"slliw", Format::I_SHIFT}, {"sllw", Format::R},
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{"slt", Format::R}, {"slti", Format::I},
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{"sltiu", Format::I}, {"sltu", Format::R},
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{"sra", Format::R}, {"srai", Format::I_SHIFT},
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{"sraiw", Format::I_SHIFT}, {"sraw", Format::R},
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{"srl", Format::R}, {"srli", Format::I_SHIFT},
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{"srliw", Format::I_SHIFT}, {"srlw", Format::R},
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{"sub", Format::R}, {"subw", Format::R},
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{"sw", Format::S}, {"xor", Format::R},
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static constexpr std::array<OpDef, 88> OP_TABLE = {{
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{"???", Format::NONE},
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{"add", Format::R},
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{"addi", Format::I},
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{"addiw", Format::I},
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{"addw", Format::R},
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{"and", Format::R},
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{"andi", Format::I},
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{"auipc", Format::U},
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{"beq", Format::B},
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{"bge", Format::B},
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{"bgeu", Format::B},
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{"blt", Format::B},
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{"bltu", Format::B},
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{"bne", Format::B},
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{"c.add", Format::CR},
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{"c.addi", Format::CI},
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{"c.addiw", Format::CI},
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{"c.addi16sp", Format::CI},
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{"c.addi4spn", Format::CI},
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{"c.beqz", Format::B},
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{"c.bnez", Format::B},
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{"c.ebreak", Format::CR},
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{"c.fldsp", Format::CSS},
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{"c.jalr", Format::CR},
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{"c.ld", Format::CL},
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{"c.ldsp", Format::CL},
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{"c.li", Format::CI},
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{"c.lui", Format::CI},
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{"c.lw", Format::CL},
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{"c.mv", Format::CR},
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{"c.sd", Format::S},
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{"c.sdsp", Format::CSS},
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{"c.slli", Format::CI},
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{"c.sw", Format::S},
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{"div", Format::R},
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{"divu", Format::R},
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{"divuw", Format::R},
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{"divw", Format::R},
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{"ecall", Format::NONE},
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{"fence", Format::NONE},
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{"fence.tso", Format::NONE},
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{"jal", Format::J},
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{"jalr", Format::I},
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{"lb", Format::I_LOAD},
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{"lbu", Format::I_LOAD},
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{"ld", Format::I_LOAD},
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{"lh", Format::I_LOAD},
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{"lhu", Format::I_LOAD},
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{"lr.d", Format::R_ATOMIC_LR},
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{"lui", Format::U},
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{"lw", Format::I_LOAD},
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{"lwu", Format::I_LOAD},
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{"mul", Format::R},
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{"mulh", Format::R},
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{"mulhu", Format::R},
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{"mulw", Format::R},
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{"or", Format::R},
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{"ori", Format::I},
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{"pause", Format::NONE},
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{"rem", Format::R},
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{"remu", Format::R},
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{"remuw", Format::R},
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{"remw", Format::R},
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{"sb", Format::S},
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{"sc.d", Format::R_ATOMIC},
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{"sd", Format::S},
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{"sh", Format::S},
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{"sll", Format::R},
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{"slli", Format::I_SHIFT},
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{"slliw", Format::I_SHIFT},
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{"sllw", Format::R},
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{"slt", Format::R},
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{"slti", Format::I},
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{"sltiu", Format::I},
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{"sltu", Format::R},
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{"sra", Format::R},
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{"srai", Format::I_SHIFT},
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{"sraiw", Format::I_SHIFT},
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{"sraw", Format::R},
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{"srl", Format::R},
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{"srli", Format::I_SHIFT},
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{"srliw", Format::I_SHIFT},
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{"srlw", Format::R},
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{"sub", Format::R},
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{"subw", Format::R},
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{"sw", Format::S},
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{"xor", Format::R},
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{"xori", Format::I},
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}};
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@@ -210,26 +297,33 @@ public:
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}
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elf_end(elf);
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u64 num_ins = m_code_section.size / 4;
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u64 num_ins = m_code_section.size / 2;
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m_decoded.resize(num_ins);
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for (u64 i = 0; i < num_ins; i++) {
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u64 offset = 0;
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while (offset < m_code_section.size) {
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u32 raw;
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std::memcpy(&raw, m_memory + m_code_section.offset + i * 4, sizeof(raw));
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m_decoded[i] = decode_raw(raw);
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std::memcpy(&raw, m_memory + m_code_section.offset + offset, sizeof(raw));
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Ins ins = decode_raw(raw);
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ins.length = ((raw & 0b11) == 0b11) ? 4 : 2;
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m_decoded[offset / 2] = ins;
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offset += ins.length;
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}
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}
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~RISCV64() { munmap(m_memory, MEMORY_SIZE); }
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void disassemble_all() {
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for (m_pc = m_code_section.offset;
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m_pc < m_code_section.offset + m_code_section.size; m_pc += 4) {
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m_pc = m_code_section.offset;
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while (m_pc < m_code_section.offset + m_code_section.size) {
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disassemble_one();
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}
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}
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void disassemble_one() {
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Ins ins = m_decoded[(m_pc - m_code_section.offset) / 4];
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Ins ins = m_decoded[(m_pc - m_code_section.offset) / 2];
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const OpDef &def = OP_TABLE[ins.op];
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@@ -273,10 +367,23 @@ public:
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case Format::CR:
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std::println("{} {}, {}", def.mnemonic, REGS[ins.rd], REGS[ins.rs2]);
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break;
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case Format::CL:
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std::println("{} {}, {}({})", def.mnemonic, REGS[ins.rd], ins.imm,
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REGS[ins.rs1]);
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break;
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case Format::R_ATOMIC_LR:
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std::println("{} {}, ({})", def.mnemonic, REGS[ins.rd], REGS[ins.rs1]);
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break;
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case Format::R_ATOMIC:
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std::println("{} {}, {}, ({})", def.mnemonic, REGS[ins.rd], REGS[ins.rs2],
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REGS[ins.rs1]);
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break;
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case Format::NONE:
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std::println("{}", def.mnemonic);
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break;
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}
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m_pc += ins.length;
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}
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void dump() {
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@@ -321,7 +428,7 @@ public:
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while (m_pc < MEMORY_SIZE) {
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m_regs[0] = 0; // clear the zero register
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Ins i = m_decoded[(m_pc - m_code_section.offset) / 4];
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Ins i = m_decoded[(m_pc - m_code_section.offset) / 2];
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switch (i.op) {
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case Op::INVALID: {
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@@ -667,7 +774,7 @@ public:
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}; break;
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}
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m_pc += 4;
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m_pc += i.length;
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}
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}
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@@ -736,6 +843,32 @@ private:
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(((raw >> 6) & 0b1) << 2) | (((raw >> 5) & 0b1) << 3);
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i.op = Op::C_ADDI4SPN;
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}; break;
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case 0b010: {
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i.rd = ((raw >> 2) & 0b111) + 8;
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i.rs1 = ((raw >> 7) & 0b111) + 8;
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i.imm = (((raw >> 10) & 0b111) << 3) | (((raw >> 6) & 0b1) << 2) |
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(((raw >> 5) & 0b1) << 6);
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i.op = Op::C_LW;
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}; break;
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case 0b011: {
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i.rd = ((raw >> 2) & 0b111) + 8;
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i.rs1 = ((raw >> 7) & 0b111) + 8;
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i.imm = (((raw >> 10) & 0b111) << 3) | (((raw >> 5) & 0b11) << 6);
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i.op = Op::C_LD;
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}; break;
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case 0b110: {
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i.rs1 = ((raw >> 7) & 0b111) + 8;
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i.rs2 = ((raw >> 2) & 0b111) + 8;
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i.imm = (((raw >> 10) & 0b111) << 3) | (((raw >> 6) & 0b1) << 2) |
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(((raw >> 5) & 0b1) << 6);
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i.op = Op::C_SW;
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}; break;
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case 0b111: {
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i.rs1 = ((raw >> 7) & 0b111) + 8;
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i.rs2 = ((raw >> 2) & 0b111) + 8;
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i.imm = (((raw >> 10) & 0b111) << 3) | (((raw >> 5) & 0b11) << 6);
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i.op = Op::C_SD;
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}; break;
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default: {
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std::println(stderr, "C: opcode=00: unrecognized funct3: {:03b}",
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funct3);
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@@ -750,6 +883,12 @@ private:
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i.imm = (i.imm << 26) >> 26;
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i.op = Op::C_ADDI;
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}; break;
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case 0b001: {
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i.rs1 = i.rd;
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i.imm = ((raw >> 2) & 0b11111) | (((raw >> 12) & 0b1) << 5);
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i.imm = (i.imm << 26) >> 26;
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i.op = Op::C_ADDIW;
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}; break;
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case 0b010: {
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i.imm = ((raw >> 2) & 0b11111) | (((raw >> 12) & 0b1) << 5);
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i.imm = (i.imm << 26) >> 26;
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@@ -769,6 +908,24 @@ private:
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}
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}; break;
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case 0b110: {
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i.rs1 = ((raw >> 7) & 0b111) + 8;
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i.rs2 = 0;
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i.imm = (((raw >> 12) & 0b1) << 8) | (((raw >> 10) & 0b11) << 3) |
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(((raw >> 5) & 0b11) << 6) | (((raw >> 3) & 0b11) << 1) |
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(((raw >> 2) & 0b1) << 5);
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i.imm = (i.imm << 23) >> 23;
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i.op = Op::C_BEQZ;
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}; break;
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case 0b111: {
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i.rs1 = ((raw >> 7) & 0b111) + 8;
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i.rs2 = 0;
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i.imm = (((raw >> 12) & 0b1) << 8) | (((raw >> 10) & 0b11) << 3) |
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(((raw >> 5) & 0b11) << 6) | (((raw >> 3) & 0b11) << 1) |
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(((raw >> 2) & 0b1) << 5);
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i.imm = (i.imm << 23) >> 23;
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i.op = Op::C_BNEZ;
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}; break;
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default: {
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std::println(stderr, "C: opcode=01: unrecognized funct3: {:03b}",
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funct3);
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@@ -782,9 +939,18 @@ private:
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i.imm = ((raw >> 2) & 0b11111) | (((raw >> 12) & 0b1) << 5);
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i.op = Op::C_SLLI;
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}; break;
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case 0b010: {
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std::println(stderr, "F extension not implemented yet.");
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exit(1);
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case 0b001: {
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i.rs1 = 2;
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i.imm = (((raw >> 12) & 0b1) << 5) | (((raw >> 5) & 0b11) << 3) |
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(((raw >> 2) & 0b111) << 6);
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i.op = Op::C_FLDSP;
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}; break;
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case 0b011: {
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i.rs1 = 2;
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i.rd = (raw >> 7) & 0b11111;
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i.imm = (((raw >> 12) & 0b1) << 5) | (((raw >> 5) & 0b11) << 3) |
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(((raw >> 2) & 0b111) << 6);
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i.op = Op::C_LDSP;
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}; break;
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case 0b100: {
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bool bit12 = (raw >> 12) & 0b1;
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@@ -801,9 +967,19 @@ private:
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i.op = Op::C_MV;
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}
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} else {
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std::println(stderr,
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"C: opcode=10: funct3=100: bit12=1: unimplemented");
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exit(1);
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if (i.rs2 == 0) {
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if (i.rd == 0) {
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i.op = Op::C_EBREAK;
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} else {
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i.rs1 = i.rd;
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i.rd = 1;
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i.imm = 0;
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i.op = Op::C_JALR;
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}
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} else {
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i.rs1 = i.rd;
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i.op = Op::C_ADD;
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}
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}
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}; break;
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case 0b111: {
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@@ -1075,9 +1251,33 @@ private:
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exit(1);
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}
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}; break;
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case 0b0101111:
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std::println(stderr, "A extension not implemented yet.");
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case 0b0101111: {
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u8 funct3 = (raw >> 12) & 0b111;
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u8 funct7 = (raw >> 27) & 0b11111;
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i.rd = (raw >> 7) & 0b11111;
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i.rs1 = (raw >> 15) & 0b11111;
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i.rs2 = (raw >> 20) & 0b11111;
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if (funct3 == 0b011) {
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switch (funct7) {
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case 0b00010: {
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i.op = Op::LR_D;
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}; break;
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case 0b00011: {
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i.op = Op::SC_D;
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}; break;
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default: {
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std::println(stderr,
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"0101111: funct3=011: unrecognized funct7: {:05b}",
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funct7);
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exit(1);
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}; break;
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}
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} else {
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std::println(stderr, "0101111: unrecognized funct3: {:03b}", funct3);
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||||
exit(1);
|
||||
}
|
||||
}; break;
|
||||
case 0b0111011: {
|
||||
u8 funct3 = (raw >> 12) & 0b111;
|
||||
u8 funct7 = (u8)((raw >> 25) & 0b1111111);
|
||||
@@ -1178,7 +1378,7 @@ private:
|
||||
} else if (funct3 == 0b011) {
|
||||
i.op = Op::SD;
|
||||
} else {
|
||||
std::println(stderr, "S-type: unrecognized funct3: {:03b}", funct3);
|
||||
std::println(stderr, "0100011: unrecognized funct3: {:03b}", funct3);
|
||||
exit(1);
|
||||
}
|
||||
}; break;
|
||||
@@ -1192,6 +1392,23 @@ private:
|
||||
i.imm = raw >> 12;
|
||||
i.op = Op::AUIPC;
|
||||
}; break;
|
||||
case 0b0001111: {
|
||||
u8 funct3 = (raw >> 12) & 0b111;
|
||||
if (funct3 == 0b000) {
|
||||
i.imm = (raw >> 20) & 0b111111111111;
|
||||
|
||||
if (i.imm == 0b000000010000) {
|
||||
i.op = Op::PAUSE;
|
||||
} else if (i.imm == 0b100000110011) {
|
||||
i.op = Op::FENCE_TSO;
|
||||
} else {
|
||||
i.op = Op::FENCE;
|
||||
}
|
||||
} else {
|
||||
std::println(stderr, "0001111: unrecognized funct3: {:03b}", funct3);
|
||||
exit(1);
|
||||
}
|
||||
}; break;
|
||||
default:
|
||||
std::println(stderr, "Unrecognized opcode: {:07b}", opcode);
|
||||
exit(1);
|
||||
|
||||
Reference in New Issue
Block a user